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CDB8422
When the evaluation board is not connected to a PC, the CS8422 is placed in hardware mode and is con-
figured using DIP switches. Certain switch settings require a board reset to take affect, see Section 3.3 for
more information.
1.5
1.6
1.7
1.8
CS8406 Digital Audio Transmitter
A complete description of the CS8406 transmitter and a discussion of the digital audio interface can be
found in the CS8406 data sheet.
The CS8406 converts the output PCM data stream from the CS8422 into S/PDIF data that is output to the
optical (J28) and RCA (J27) connectors. In software mode, device configuration pins are controlled by using
the “FPGA Controls” tab of the Cirrus FlexGUI software, see Section 2.3 for details.
CS8422 XTI Sources
The CS8422 XTI clock source is selected by jumper J23. The clock signal may be provided by the socketed
on-board canned oscillator (Y1), socketed on-board parallel resonant crystal (Y2), or input serial header
J22. The oscillator and crystal are mounted in pin sockets, allowing for easy removal and replacement. The
device footprint on the board for Y1 will only accommodate half-can-sized oscillators. Section 5 describes
which jumper position selects each clock source.
I/O Stake Headers
The evaluation board has been designed to allow interfacing with external systems via several serial port
headers and a control port header (J26). The input serial port header (J22) provides access to the input se-
rial audio port of the CS8422. The output serial port headers provide access to both output serial audio
port 1 (J24) and output serial audio port 2 (J25) of the CS8422. All three serial port headers can be placed
in master or slave mode with respect to the CS8422. The TDM input header (J30) allows TDM data to be
input from another system into the CS8422.
The control port header provides bidirectional access to the I2C or SPI control port signals by simply remov-
ing all the shunts from the “PC Control” position. The user may then connect a ribbon cable connector to
the “External Connection” pins for external control of board functions. A single row of “GND” pins is provided
to maintain signal ground integrity. Two unpopulated pull-up resistors are also available should the user
choose to use the CDB8422 logic supply (VL) externally.
S/PDIF and AES3/EBU Inputs
The CDB8422 allows for both S/PDIF and AES3/EBU input signals to be connected to the CS8422. Four
pairs of optical and RCA connectors are provided to connect single-ended S/PDIF signals to the four receiv-
er ports on the CS8422. A single XLR connector is provided to connect a differential AES3/EBU signal to
either of the two differential receiver ports on the CS8422.
Figure 16 illustrates how the S/PDIF and AES3/EBU inputs are connected and routed. Table 7 details the
associated jumper selections. The CS8422 data sheet specifies the maximum allowed input voltage levels.
Note that, as a result of signal attenuation resulting from PCB parasitics, the input S/PDIF signal amplitude
at the receiver input pins of the CS8422 may be lower than at the input connectors. See the CS8422 data
sheet for the minimum signal amplitude required at the receiver input pins of the CS8422.
DS692DB2
5
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